This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits may be configured with general purpose input/output (GPIO) pins to provide chip designers with access to available digital control lines. Even though GPIO pins may not have a predefined purpose, these unused GPIO pins are available by default. Thus, chip designers building a system on a chip (SoC) may use these available GPIO pins as digital control lines so as to avoid having to arrange additional circuitry on a chip to provide for digital control lines.
FIG. 1 shows a diagram of a conventional GPIO receiver circuitry 100. The conventional GPIO receiver circuitry 100 uses input stages PAD, PADB that are common for Schmitt mode (slow slew) as well as CMOS mode (fast slew). Unfortunately, this GPIO receiver circuitry 100 is deficient and lacks performance due to power being wasted during Schmitt mode (slow slew). As shown in FIG. 1, when PAD is rising from 0V to DVDD, and when PAD is at Vih, transistors N1, N2 turn ON completely, and PADB becomes 0V (or DVSS, near ground voltage GND). At this time, transistor P3 is turned on, and when PAD input reaches from Vih to DVDD, there is a current path from DVDD to DVSS through transistors P1 and P3.
Similarly, when PAD is coming back from DVDD to 0V, and when PAD is at Vil, switching happens, and PADB becomes DVDD. At this time, transistor N3 turns ON, so from PAD reaching Vil to 0V, there is a current path from DVDD to DVSS through the transistors N3 and N1. These two current paths (or current deviations) are configured to generate or create hysteresis by delaying the threshold when PAD input rises or falls, from DVDD to DVSS. In some cases, similar problems may arise when PAD input is at Vih/Vil level or even when input and receiver supply are at upper and lower boundaries of IO (input/output) supply (DVDD), respectively.